Electronic devices, such as tablets, computers, server, in-door telecom, out-door telecom, industrial computers, high performance computing data centers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip packages for increased functionality and higher component density. Conventional chip packages include one or more stacked components such as integrated circuit (IC) dies, through-silicon-via (TSV) interposer, and a package substrate, with the chip package itself stacked on a printed circuit board (PCB). The IC dies may include memory, logic, MEMS, RF or other IC device.
In many chip packages, providing adequate thermal management has become increasingly challenging. Failure to provide adequate cooling often results in diminished service life and even device failure. Thermal management is particularly problematic in applications where high bandwidth memory (HBM) stacks and logic die, such as field programmable gate arrays (FPGA), are integrated in a single package. In such applications, the height differential between the HBM stack and logic die may result in inefficient cooling due to excessive use of thermal interface material or overmolding to compensate for the height mismatch. Failure to adequately regulate the temperature of the chip package may also result in diminished performance, device failure or system shutdowns. Furthermore, a large height differential between the HBM stack and logic die also creates a variety of assembly and factory automation problems, which undesirably contribute to poor production yields and longer, and thus more costly, fabrication times.
Therefore, a need exists for an improved chip package for co-packaged logic and memory applications.